IP PortfolioVerification IPdebug interface vip
of_vip_swd_bfm
Serial Wire Debug bus functional model and agent
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
SWD host agent issuing debug port and access port reads and writes with WAIT and FAULT handling.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| swclk | out | clock | 1 | |
| swdio | inout | serial | 1 |
Standards
- Arm ADIv5
More in debug interface vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_jtag_mon | JTAG monitor and protocol checker | simulated |
| of_vip_jtag_bfm | JTAG bus functional model and agent | simulated |
| of_vip_swd_mon | Serial Wire Debug monitor and protocol checker | planned |