IP PortfolioVerification IPdebug interface vip
of_vip_jtag_mon
JTAG monitor and protocol checker
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
JTAG monitor tracking the TAP state machine and decoding IR and DR scans against a BSDL description.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 5 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- IEEE 1149.1
- IEEE 1149.6
More in debug interface vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_jtag_bfm | JTAG bus functional model and agent | simulated |
| of_vip_swd_mon | Serial Wire Debug monitor and protocol checker | planned |
| of_vip_swd_bfm | Serial Wire Debug bus functional model and agent | planned |