of_cpu_hpm_counters
Performance monitor counters
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Hardware performance monitor with configurable event selection, privilege filtering and overflow interrupts.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| irq | out | interrupt | 1 | Interrupt request |
| events | in | parallel | 64 |
Standards
- RISC-V Sscofpmf
- RISC-V Smcntrpmf
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_debug_module | RISC-V debug module | simulated |
| of_cpu_jtag_dtm | JTAG debug transport module | fpga-routed |
| of_cpu_trigger_module | Debug trigger module | planned |
| of_cpu_cross_trigger | Multicore cross-trigger matrix | planned |
| of_cpu_ras_reri | RAS error record unit | planned |
| of_cpu_pc_profiler | PC sampling profiler | planned |