of_cpu_pc_profiler
PC sampling profiler
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Non-intrusive profiler that samples retired program counters and branch history into a buffer for statistical profiling without halting the hart.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| retire_pc | in | valid-qualified bus | 64 |
Standards
No external standard applies.
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_debug_module | RISC-V debug module | simulated |
| of_cpu_jtag_dtm | JTAG debug transport module | fpga-routed |
| of_cpu_trigger_module | Debug trigger module | planned |
| of_cpu_cross_trigger | Multicore cross-trigger matrix | planned |
| of_cpu_hpm_counters | Performance monitor counters | planned |
| of_cpu_ras_reri | RAS error record unit | planned |