of_cpu_ras_reri
RAS error record unit
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Error record banks with standard register layout for logging and signalling corrected and uncorrected hardware errors.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| err_in | in | valid-qualified bus | 64 |
Standards
- RISC-V RERI 1.0
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_debug_module | RISC-V debug module | simulated |
| of_cpu_jtag_dtm | JTAG debug transport module | fpga-routed |
| of_cpu_trigger_module | Debug trigger module | planned |
| of_cpu_cross_trigger | Multicore cross-trigger matrix | planned |
| of_cpu_hpm_counters | Performance monitor counters | planned |
| of_cpu_pc_profiler | PC sampling profiler | planned |