of_cpu_jtag_dtm
JTAG debug transport module
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
JTAG TAP and debug transport module bridging IEEE 1149.1 (and optionally the two-pin IEEE 1149.7) to the debug module interface.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| jtag | in | parallel | 4 | |
| tdo | out | serial | 1 | |
| dmi | out | valid-qualified bus | 41 |
Standards
- IEEE 1149.1
- IEEE 1149.7
- RISC-V Debug 0.13
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_debug_module | RISC-V debug module | simulated |
| of_cpu_trigger_module | Debug trigger module | planned |
| of_cpu_cross_trigger | Multicore cross-trigger matrix | planned |
| of_cpu_hpm_counters | Performance monitor counters | planned |
| of_cpu_ras_reri | RAS error record unit | planned |
| of_cpu_pc_profiler | PC sampling profiler | planned |