of_cpu_l1d_cache
L1 data cache
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Non-blocking write-back data cache with MSHRs, store buffer, ECC, atomic memory operation support and cache-block management operations.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| lsu_req | in | valid-qualified bus | 140 | |
| lsu_rsp | out | valid-qualified bus | 72 |
Standards
- RISC-V Zicbom
- RISC-V Zicboz
- RISC-V A
More in cache
| ID | Block | Maturity |
|---|---|---|
| of_cpu_l1i_cache | L1 instruction cache | simulated |
| of_cpu_l2_cache | Shared L2 cache | planned |
| of_cpu_llc_partitioned | Last-level cache slice with QoS | planned |
| of_cpu_prefetcher | Hardware data prefetcher | planned |
| of_cpu_tcm_ctrl | Tightly coupled memory controller | simulated |
| of_cpu_xip_cache | Execute-in-place flash cache | planned |