of_cpu_tcm_ctrl
Tightly coupled memory controller
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Single-cycle instruction and data TCM controller with ECC, a slave port for DMA access and configurable banking.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in cache
| ID | Block | Maturity |
|---|---|---|
| of_cpu_l1i_cache | L1 instruction cache | simulated |
| of_cpu_l1d_cache | L1 data cache | planned |
| of_cpu_l2_cache | Shared L2 cache | planned |
| of_cpu_llc_partitioned | Last-level cache slice with QoS | planned |
| of_cpu_prefetcher | Hardware data prefetcher | planned |
| of_cpu_xip_cache | Execute-in-place flash cache | planned |