of_cpu_llc_partitioned
Last-level cache slice with QoS
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Last-level cache slice with way partitioning, capacity and bandwidth monitoring and allocation controls for shared datacenter SoCs.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- RISC-V CBQRI 1.0
More in cache
| ID | Block | Maturity |
|---|---|---|
| of_cpu_l1i_cache | L1 instruction cache | simulated |
| of_cpu_l1d_cache | L1 data cache | planned |
| of_cpu_l2_cache | Shared L2 cache | planned |
| of_cpu_prefetcher | Hardware data prefetcher | planned |
| of_cpu_tcm_ctrl | Tightly coupled memory controller | simulated |
| of_cpu_xip_cache | Execute-in-place flash cache | planned |