of_cpu_xip_cache
Execute-in-place flash cache
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Read cache with prefetch and optional decryption hook in front of a serial NOR flash controller for execute-in-place firmware.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in cache
| ID | Block | Maturity |
|---|---|---|
| of_cpu_l1i_cache | L1 instruction cache | simulated |
| of_cpu_l1d_cache | L1 data cache | planned |
| of_cpu_l2_cache | Shared L2 cache | planned |
| of_cpu_llc_partitioned | Last-level cache slice with QoS | planned |
| of_cpu_prefetcher | Hardware data prefetcher | planned |
| of_cpu_tcm_ctrl | Tightly coupled memory controller | simulated |