IP PortfolioSoC interconnectdma
of_dma_mcu
MCU peripheral DMA
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Low-gate-count AHB DMA with 4 to 16 channels triggered by peripheral requests, fixed or incrementing addresses, circular mode and half/full transfer interrupts.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| m_ahb | out | valid-qualified bus | 96 | |
| dreq | in | parallel | 16 |
Standards
- AMBA AHB5
More in dma
| ID | Block | Maturity |
|---|---|---|
| of_dma_sg | Scatter-gather DMA controller | simulated |
| of_dma_nd | Multi-dimensional (2D/3D) DMA | planned |
| of_dma_stream | AXI4-Stream DMA (MM2S / S2MM) | simulated |