IP PortfolioSoC interconnectdma
of_dma_stream
AXI4-Stream DMA (MM2S / S2MM)
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Simple register-programmed DMA moving packets between AXI4 memory and AXI4-Stream in both directions, with buffer descriptors and packet length reporting.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
| m_axis | out | AXI4-Stream | 64 | |
| s_axis | in | AXI4-Stream | 64 |
Standards
- AMBA AXI4
- AMBA AXI4-Stream
Basis projects
Permissive open projects the implementation may build on.
- verilog-axi (MIT)
More in dma
| ID | Block | Maturity |
|---|---|---|
| of_dma_sg | Scatter-gather DMA controller | simulated |
| of_dma_nd | Multi-dimensional (2D/3D) DMA | planned |
| of_dma_mcu | MCU peripheral DMA | planned |