IP PortfolioSoC interconnectdma
of_dma_nd
Multi-dimensional (2D/3D) DMA
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
DMA engine with up to three nested strided loops per descriptor for image tiles, matrix blocks and tensor slices, with independent source and destination strides.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA AXI4
More in dma
| ID | Block | Maturity |
|---|---|---|
| of_dma_sg | Scatter-gather DMA controller | simulated |
| of_dma_stream | AXI4-Stream DMA (MM2S / S2MM) | simulated |
| of_dma_mcu | MCU peripheral DMA | planned |