of_dma_sg

Scatter-gather DMA controller

Maturity simulatedTargets FPGA + ASICDifficulty HardPriority 1

Multi-channel AXI4 DMA with linked-list descriptors in memory, memory-to-memory, memory-to-stream and stream-to-memory transfers, per-channel priority and completion interrupts.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
m_axi	out	valid-qualified bus	256	AXI4 master port (AW/W/AR channels)
m_axis	out	AXI4-Stream	64
s_axis	in	AXI4-Stream	64

Standards

AMBA AXI4

More in dma

ID	Block	Maturity
of_dma_nd	Multi-dimensional (2D/3D) DMA	planned
of_dma_stream	AXI4-Stream DMA (MM2S / S2MM)	simulated
of_dma_mcu	MCU peripheral DMA	planned