IP PortfolioSoC interconnecttimers
of_timer
Programmable timer / counter with prescaler
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Down-counting timer with programmable prescaler, reload value, one-shot or periodic (auto-reload) mode and an external-event counting mode; expired pulses once per interval.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
No external interfaces are defined for this entry yet.
Standards
No external standard applies.
More in timers
| ID | Block | Maturity |
|---|---|---|
| of_watchdog | Windowed watchdog timer | fpga-routed |
| of_aclint | RISC-V ACLINT | simulated |
| of_rtc | Real-time clock and calendar | planned |
| of_timestamp | Global timestamp generator | planned |
| of_timer_multi | Multi-channel general-purpose timer | planned |