IP PortfolioSoC interconnectdebug and trace
of_rv_dtm
RISC-V JTAG debug transport module
Maturity fpga-routedTargets FPGA + ASICDifficulty MediumPriority 1
JTAG debug transport module exposing the debug module interface through IEEE 1149.1 instructions DTMCS and DMI.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tck | in | clock | 1 | |
| tms | in | serial | 1 | |
| tdi | in | serial | 1 | |
| tdo | out | serial | 1 | |
| dmi | out | valid-qualified bus | 41 |
Standards
- RISC-V Debug Specification 1.0
- IEEE 1149.1
Basis projects
Permissive open projects the implementation may build on.
- PULP riscv-dbg (SHL-0.51)
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |
| of_uart_bus_bridge | UART to bus debug bridge | planned |