IP PortfolioSoC interconnectdebug and trace
of_rv_etrace
RISC-V E-Trace encoder
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Instruction trace encoder producing compressed branch trace packets from the core retirement interface, with filtering and timestamps.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| itrace | in | valid-qualified bus | 128 | |
| m_trace | out | AXI4-Stream | 32 |
Standards
- RISC-V Efficient Trace (E-Trace) 2.0
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |
| of_uart_bus_bridge | UART to bus debug bridge | planned |