IP PortfolioSoC interconnectdebug and trace
of_rv_ntrace
RISC-V N-Trace encoder
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Nexus-message-based instruction trace encoder with branch history, ownership and error messages for RISC-V harts.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| itrace | in | valid-qualified bus | 128 | |
| m_trace | out | AXI4-Stream | 32 |
Standards
- RISC-V N-Trace
- IEEE-ISTO 5001
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |
| of_uart_bus_bridge | UART to bus debug bridge | planned |