IP PortfolioSoC interconnectdebug and trace
of_uart_bus_bridge
UART to bus debug bridge
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Simple framed command protocol over UART that performs reads and writes on an AXI4-Lite or Wishbone bus for board bring-up.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| rxd | in | serial | 1 | |
| txd | out | serial | 1 | |
| m_axil | out | valid-qualified bus | 128 |
Standards
No external standard applies.
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |