IP PortfolioSoC interconnecttimers
of_aclint
RISC-V ACLINT
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Machine timer (MTIMER), machine software interrupt (MSWI) and supervisor software interrupt (SSWI) devices with a SiFive CLINT compatible register layout option.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| mtip | out | parallel | 8 | |
| msip | out | parallel | 8 | |
| rtc_tick | in | parallel | 1 |
Standards
- RISC-V ACLINT
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in timers
| ID | Block | Maturity |
|---|---|---|
| of_timer | Programmable timer / counter with prescaler | fpga-routed |
| of_watchdog | Windowed watchdog timer | fpga-routed |
| of_rtc | Real-time clock and calendar | planned |
| of_timestamp | Global timestamp generator | planned |
| of_timer_multi | Multi-channel general-purpose timer | planned |