IP PortfolioSoC interconnecttimers
of_timer_multi
Multi-channel general-purpose timer
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Bank of 32-bit timers with prescalers, input capture, output compare, PWM and cascade modes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| cap_in | in | parallel | 4 | |
| cmp_out | out | parallel | 4 |
Standards
No external standard applies.
More in timers
| ID | Block | Maturity |
|---|---|---|
| of_timer | Programmable timer / counter with prescaler | fpga-routed |
| of_watchdog | Windowed watchdog timer | fpga-routed |
| of_aclint | RISC-V ACLINT | simulated |
| of_rtc | Real-time clock and calendar | planned |
| of_timestamp | Global timestamp generator | planned |