of_rtc

Real-time clock and calendar

Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2

Always-on RTC with seconds counter, BCD calendar, alarms, periodic wakeup and 32.768 kHz crystal trim calibration.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
clk_32k	in	clock	1

Standards

No external standard applies.

More in timers

ID	Block	Maturity
of_timer	Programmable timer / counter with prescaler	fpga-routed
of_watchdog	Windowed watchdog timer	fpga-routed
of_aclint	RISC-V ACLINT	simulated
of_timestamp	Global timestamp generator	planned
of_timer_multi	Multi-channel general-purpose timer	planned