IP PortfolioSoC interconnecttimers
of_timestamp
Global timestamp generator
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
64-bit system timestamp counter distributed to multiple clock domains via Gray-coded or narrow encoded buses, for trace and time synchronization.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| ts_out | out | parallel | 64 |
Standards
No external standard applies.
More in timers
| ID | Block | Maturity |
|---|---|---|
| of_timer | Programmable timer / counter with prescaler | fpga-routed |
| of_watchdog | Windowed watchdog timer | fpga-routed |
| of_aclint | RISC-V ACLINT | simulated |
| of_rtc | Real-time clock and calendar | planned |
| of_timer_multi | Multi-channel general-purpose timer | planned |